A continuing object of high performance semiconductor manufacturers is to increase power and speed of a semiconductor device while keeping device size to a minimum. However by increasing device and system density to reduce size, electrical performance of the device is often adversely affected. For instance, inductance of an integrated circuit and a device package can induce spurious voltage spikes in a power supply system which can in turn couple to signal leads of the device and cause timing problems in signal switching.
A common method of negating the effects of inductance and rapid voltage changes in a device is to use a decoupling capacitor. Decoupling capacitors shunt power and ground planes or power and ground leads so that rapid voltage changes in the device result in an electrical short circuit across the capacitor, translating voltage spikes into a stored charge on the decoupling capacitor. The stored charge either dissipates or is used as a local power supply to device inputs during subsequent signal switching stages, allowing the decoupling capacitor to negate the effects of voltage noise induced into the system by parasitic inductance.
One way in which decoupling capacitors have been used in the past is by mounting a discrete decoupling capacitor next to a semiconductor device on a substrate, such as a PC board. Conductive traces on the substrate are used to electrically couple the decoupling capacitor to power and ground pins of the semiconductor device. Another approach is to attach a discrete decoupling capacitor directly to the face of a semiconductor die such that the decoupling capacitor is electrically coupled to power and ground bond pads of the die or to power and ground leads. Yet another technique is to electrically couple a discrete decoupling capacitor to adjacent power and ground leads of a tape automated bonding (TAB) device.
Each of the known methods of using decoupling capacitors mentioned above serves to negate the effects of rapid voltage swings in a semiconductor device to a degree. However, a disadvantage of some known decoupling capacitors is that the capacitors require additional area on a substrate or increase the size of a semiconductor device. Therefore, many of the decoupling capacitors currently in use go against a primary objective of semiconductor manufacturers and users to reduce device size and area. Another disadvantage with some known decoupling capacitors is that an undesirable amount of inductance is associated with the interconnection between the semiconductor die and the decoupling capacitor. For this reason, it is desirable to have a decoupling capacitor which is as close to the die as possible in order to shorten the interconnection distance, thereby lowering inductance. An additional disadvantage with some known methods of employing a decoupling capacitor is that not all power and ground leads are electrically coupled to the capacitor. Therefore, rapid voltage swings in a device are not countered fast enough or are not countered as effectively as desired.